1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same, and particularly to a structure of a dynamic random access memory (DRAM) and a manufacturing method of the same.
2. Description of the Related Art
In recent years, demand for semiconductor memory devices has rapidly increased owing to remarkably widened use of information equipments such as computers. Further, with respect to functions, there have been demanded semiconductor memory devices having large storage capacities and capable of high-speed operations. In compliance with this, technical development for high integration, high responsibility and high reliability of the semiconductor memory devices has been advanced.
DRAMs (dynamic random access memories) are known as the semiconductor memory devices which allow random input and output of stored information. Generally, the DRAM is formed of a memory cell array part which is a memory region storing a large amount of information, and a peripheral circuit part which is necessary for external input and output.
FIG. 61 is a block diagram showing a general structure of a DRAM. Referring to FIG. 61, a DRAM 150 includes a memory cell array 151, a row and column address buffer 152 for externally receiving an address signal which is used for selecting a memory cell forming a unit memory circuit, row and column decoders 153 and 154 which decode the address signal to designate a memory cell, a sense refresh amplifier 155 which amplifies the signal stored in the designated memory cell to read the same, data-in and data-out buffers 156 and 157 for input and output of the data, and a clock generator 158 for generating a clock signal.
Memory cell array 151, which occupies a large area on a semiconductor chip, is formed of a plurality of memory cells each storing unit memory information disposed in a matrix. Each memory cell is generally formed of one MOS transistor and one capacitor connected thereto. This memory cell is well known as a memory cell of one-transistor/one-capacitor type. The memory cells having such simple structures enable the highly integrated memory cell array without difficulty, so that they are widely used in the DRAMs of large capacities.
The memory cells of the DRAMs can be classified into several types depending on the structures of the capacitors. Among them, in a stacked type capacitor an opposed area between electrodes of the capacitor is increased by extending a major part of the capacitor to a position above a gate electrode and a field isolation film. The opposed area thus increased between the electrodes of the capacitor increases the capacity of the capacitor. Since the stacked type capacitor has such feature, the capacitor capacity can be ensured even if elements are miniaturized in accordance with the high integration of the semiconductor device. Consequently, the stacked type capacitors have come to be widely used accordance with the higher integration of the semiconductor devices.
FIG. 62 is a cross section showing a DRAM provided with a conventional stacked type capacitor. Referring to FIG. 62, the conventional DRAM includes a semiconductor substrate 101 as well as following components and portions. An isolating oxide film 102 for elements is formed on a predetermined region of a major surface of semiconductor substrate 101. A channel stopper layer 103 is formed under isolating oxide film 102. A pair of source/drain regions 104 and 105 are formed in a region surrounded by an isolating oxide film 102 with a channel region 106 therebetween. A gate electrode 108 is formed on channel region 106 with a gate insulating film 107 therebetween. Gate electrode 108 is covered with an interlayer insulating film 109, which is covered with an interlayer insulating film 110. A capacitor lower electrode 111 formed of polysilicon is electrically connected to source/drain region 105 and extends on and along interlayer insulating film 110. Capacitor lower electrode 111 is covered with a capacitor insulating film 112, on which a capacitor upper electrode 113 is formed. An interlayer insulating film 114 covers the whole surface and has a contact hole 114a located on source/drain region 104. A polysilicon layer 115 is electrically connected to source/drain region 104 and extends on and along a surface of an interlayer insulating film 114. A tungsten silicide layer 116 is formed on polysilicon layer 115, and is covered with an interlayer insulating film 117. An interconnection layer 118 is formed on an interlayer insulating film 117 to correspond to gate electrode 108.
Interconnection layer 118 is formed of a titanium layer 118a and an aluminum alloy layer 118b formed on titanium layer 118a. Capacitor lower electrode 111, capacitor insulating film 112 and capacitor upper electrode 113 form a capacitor for storing electric charges corresponding to a data signal. Polysilicon layer 115 and tungsten silicide layer 116 form a signal transmitting line, i.e., a bit line. Source/drain regions 104 and 105 and gate electrode 108 form a transfer gate transistor.
In a reading operation, the charges corresponding to the data signals are transmitted through a bit line (115 and 116) to source/drain region 104. By applying a predetermined voltage to gate electrode 108, the transfer gate transistor is turned on. Upon turn-on of the transfer gate transistor, the charges stored in source/drain region 104 are transmitted through channel region 106 to source/drain region 105. The charges transmitted to source/drain region 105 are stored in the capacitor (111, 112 and 113).
In the reading operation, a predetermined voltage is applied to gate electrode 108 to turn on the transfer gate transistor. Thereby, the charges stored in the capacitor (111, 112 and 113) are transmitted through capacitor lower electrode 111, source/drain region 105 and source/drain region 104 to bit line (115 and 116).
FIGS. 63-82 are cross sections showing a manufacturing process (lst to 20th steps) of the conventional DRAM shown in FIG. 62. The manufacturing process of the conventional DRAM will be described below with reference to FIG. 62 as well as FIGS. 63-82.
First, as shown in FIG. 63, an underlayer oxide film 102a is formed on P-type silicon semiconductor substrate 101. A silicon nitride film 119 is formed on underlayer oxide film 102a.
Then, as shown in FIG. 64, resist 120 is formed on a predetermined region of a silicon nitride film 119, using photolithography. Anisotropic etching is then applied, using resist 120 as a mask, for patterning silicon nitride film 119. Impurities are ion-implanted, using patterned silicon nitride film 119 and resist 120 as a mask.
Then, as shown in FIG. 65, thermal oxidation is applied, using silicon nitride film 119 as a mask, to form isolating oxide film (field oxide film) 102 and channel stopper layer 103. Thereafter, silicon nitride film 119 is removed.
Then, as shown in FIG. 66, impurities for channel doping are ion-implanted, and thereafter, underlayer oxide film 102a is removed.
Then, as shown in FIG. 67, a gate oxide film layer 107a is formed, using thermal oxidation. Impurity doped polysilicon layer 108a is formed by a CVD method or the like. Oxide film 109a is formed on gate electrode layer 108a.
Then, as shown in FIG. 68, a resist 121 is formed on a predetermined region of oxide film 109a, using photolithography. Anisotropic etching is applied, using resist 121 as a mask, to form gate electrode 108 and oxide film 109a.
Then, as shown in FIG. 69, impurities are ion-implanted, using gate electrode 108 and oxide film 109a as a mask, whereby source/drain regions 104 and 105 are formed in a self-aligned manner.
Then, as shown in FIG. 70, oxide film 109b is formed over the whole surface, using the CVD method or the like.
Then, as shown in FIG. 71, anisotropic etching is applied to the whole surface, and side walls 109b are formed in the self-aligned manner on opposite side walls of gate electrodes 108. Thereby, gate electrode 108 is covered in the self-aligned manner with insulating film 109 (109a and 109b).
Then, as shown in FIG. 72, oxide film 110 is further formed on the whole surface.
Then, as shown in FIG. 73, a resist 122 is formed on a portion of oxide film 110 except for a region located above source/drain region 105. Etching is done using resist 122 as a mask, to form a contact hole 110a through which source/drain region 105 is exposed. Impurities are ion-implanted, using contact hole 110a and resist 122 as a mask. Thereafter, resist 122 is removed.
Then, as shown in FIG. 74, a capacitor lower electrode layer 111a of polysilicon is formed on the whole surface. Impurities are ion-implanted into capacitor lower electrode layer 111a formed of polysilicon to render the same conductive.
Then, as shown in FIG. 75, a resist 123 is formed on a predetermined region of capacitor lower electrode layer 111a (see FIG. 74), using the photolithography. Anisotropic etching is done, using resist 123 as a mask, to form capacitor lower electrode 111. Thereafter, resist 123 is removed.
Then, as shown in FIG. 76, a capacitor insulating film 112a is formed on the whole surface, and thereafter, a capacitor upper electrode layer 113a of polysilicon containing doped impurity is formed on capacitor insulating film 112a.
Then, as shown in FIG. 77, a resist 124 is formed on a predetermined region of capacitor upper electrode layer 113a (see FIG. 76), using photolithography. Anisotropic etching is done, using resist 124 as a mask, to form capacitor insulating film 112 and capacitor upper electrode 113. Thereafter, resist 124 is removed.
Then, as shown in FIG. 78, interlayer insulating film 114 is formed on the whole surface. Reflow method or etch-back method is applied to planarized an upper surface of interlayer insulating film 114.
Then, as shown in FIG. 79, a resist 125 is formed on a predetermined region of interlayer insulating film 114, using photolithography. Anisotropic etching is done, using resist 125 as a mask, to form contact hole 114a, and then isotropic etching is done to form a contact hole 114b. Thereby, the surface of source/drain region 104 is exposed. Thereafter, resist 125 is removed.
Then, as shown in FIG. 80, CVD method is used to form polysilicon layer 115 on the whole surface. A sputter method is used to form tungsten silicide (WSi.sub.2) layer 116 on polysilicon layer 115. Polysilicon layer 115 and tungsten silicide layer 116 are patterned, using the photolithography, to form the bit line by polysilicon layer 115 and tungsten silicide 116.
Then, as shown in FIG. 81, interlayer insulating film 117 is formed to cover tungsten silicide layer 116. After forming titanium layer 118a on interlayer insulating film 117, using sputter method, aluminum alloy layer 118b is formed, using the sputter method.
Then, as shown in FIG. 82, a resist 126 is formed on a predetermined region of aluminum alloy layer 118b, using photolithography. Anisotropic etching is done, using the resist 126 as a mask, to form interconnection layer consisting of titanium layer 118a and aluminum alloy layer 118b. Thereafter, resist 126 is removed. Thereby, the DRAM as shown in FIG. 62 is formed.
As described above, the stacked capacitor as shown in FIG. 62 has been used in the prior art in order to ensure an intended capacitor capacity even in a case that the elements are miniaturized in accordance with the high integration of the semiconductor device.
However, it is difficult to ensure the intended capacitor capacity in the structure as shown in FIG. 62, e.g., in the DRAM of 256 Mbit, in which elements are further miniaturized.
An improvement such as described in the following has been proposed. FIG. 83 is a cross section showing a DRAM provided with an improved stacked type capacitor in the prior art. Referring to FIG. 83, the improved prior art DRAM includes a silicon semiconductor substrate 131 as well as the following components and portions. An isolating oxide film 132 for isolating elements is formed on a predetermined region of a major surface of silicon semiconductor substrate 131. A channel stopper layer 133 is formed under isolating oxide film 132. Source/drain regions 134 and 135 are formed in a region surrounded by isolating oxide film 132 and are located at opposite sides of a channel region 136 with a predetermined space therebetween. A gate electrode 138 is formed on channel region 136 with a gate insulating film 137 therebetween. Gate electrode 138 is covered with an insulating film 139. A buried bit line 140 is electrically connected to source/drain region 134 and extends on and along a surface of insulating film 139. An interlayer insulating film 141 covers the whole surface and has a contact hole 141a located above source/drain region 135. A polysilicon plug 142 is formed in contact hole 141a and is electrically connected to source/drain region 135. A platinum layer 143 extends on polysilicon plug 142 and interlayer insulating film 141. A ferroelectric film 144 containing lead such as PZT (zirconium lead titanate ceramics) or PLZT is formed on platinum layer 143. A capacitor upper electrode 145 of, e.g., platinum is formed on ferroelectric film 144. An interlayer insulating film 146 is formed to cover the whole surface and has a contact hole 146a located above capacitor upper electrode 145. An interconnection layer 147 extends on and along interlayer insulating film 146 and is electrically connected to capacitor electrode 145. Ferroelectric film 144 forms a capacitor insulating film.
FIGS. 84 to 88 are cross sectional views showing a manufacturing process of a conventional DRAM shown in FIG. 83. Referring to FIG. 83 and FIGS. 84 to 88, a manufacturing process will be described. First, as shown in FIG. 84, isolating oxide film 132 is formed on a predetermined region of a major surface of silicon semiconductor substrate 131. Channel stopper layer 133 is formed under isolating oxide film 132. Source-drain regions 134 and 135 are formed on an activated region of silicon semiconductor substrate 131, apart from each other with a predetermined space. Gate electrode 138 is formed between source-drain regions 134 and 135 on silicon semiconductor substrate 131 with gate insulating film 137 interposed therebetween. Insulating film 139 is formed to cover gate electrode 138. Buried bit line 140 is formed electrically connected to source/drain region 134 and extending on and along a surface of insulating film 139. After interlayer insulating 141 is formed, having its surface planarized so as to cover the whole surface, contact hole 141a is formed thereon reaching source/drain region 135.
A polysilicon layer 142a is formed in contact hole 141a and on an upper surface of interlayer insulating film 141 by means of the CVD method. Thereafter, polysilicon layer 142a located on the upper surface of interlayer insulating film 141 is etched back to be removed, and is further overetched for the purpose of completely removing residues caused by the etching on the upper surface of interlayer insulating film 141. Polysilicon plug 142 in a shape shown in FIG. 86 is thus obtained.
As shown in FIG. 87, a platinum layer 143a is formed on the upper surface of interlayer insulating film 141 and on a surface of silicon plug 142 in contact hole 141a utilizing the sputter method. Thereafter, as shown in FIG. 88, a ferroelectric film layer 144a of PZT or PLZT or the like is formed on platinum layer 143a by means of the sputter method, and a capacitor upper electrode layer 145a is formed thereon. Platinum layer 143a, ferroelectric film layer 144a and capacitor upper electrode layer 145a are patterned, and an interlayer insulating film 146 and an interconnection layer 147 are formed. The conventional DRAM shown in FIG. 83 can thus be obtained.
As described above, there has been proposed a DRAM in which bit line 140 is buried and the capacitor insulating film is formed of ferroelectric film 144 having a high dielectric constant in order to ensure a sufficient capacitor capacity even in a case that the elements are further miniaturized.
In this proposed DRAM, however, the following problem arises. That is, in the etching back process of polysilicon layer 142a shown in FIGS. 85 and 86, polysilicon layer 142a is overetched for completely removing residues, caused by etching, on the upper surface of interlayer insulating film 141, whereby the upper surface of polysilicon plug 142 is formed sunken in contact hole 141a. If, on the upper surface of this condition, platinum layer 143a is formed utilizing a method which cannot cover a stepped portion sufficiently, such as the sputter method, and ferroelectric film layer 144a is further formed on platinum layer 143a utilizing the sputter method, a thin portion of ferroelectric film layer 144a will be created on the stepped portion of platinum layer 143a. In this condition, formation of capacitor upper electrode layer 145a will result in a shape as shown in FIG. 88. That is, a space between platinum layer 143a and capacitor upper electrode layer 145a in the vicinity of the stepped portion of platinum layer 143a is made narrow, causing a disadvantage that an electric field applied thereon becomes stronger than that of other portions. As a result, a problem occurs that pressure-resistant and leakage-resistant characteristics as a whole capacitor are impaired.
Adhesion between interlayer insulating film 141 and capacitor lower electrode, i.e., platinum layer 143 is insufficient, so that platinum layer 143 may be disadvantageously separated. Since interconnection layer 142 is formed of polysilicon, platinum layer 143 and interconnection layer 142 may cause a silicification reaction due to a heat treatment in a later step. The silicification reaction forms an SiO.sub.2 film (not shown) having a low dielectric constant at an interface between ferroelectric film 144 and platinum layer 143. This reduces the capacitor capacity, resulting in a disadvantage that the stable operation of the memory cannot be ensured. Platinum layer 143 is essential, if ferroelectric film 144 containing the lead is used, so that the perovskite crystal structure and the high dielectric constant may be maintained.
As described above, there has been proposed a memory cell which is of the buried bit line type and uses ferroelectric film 144 to deal with the further miniaturization of the elements. The proposed memory cell, however, has various disadvantages as described above. Therefore, it is impossible to ensure a sufficient and stable capacitor capacity in the proposed prior art, if the elements are further miniaturized.